1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that has a memory cell with a buried plate-wiring.
2. Description of the Related Art
A dynamic RAM has the highest integration density of elements of semiconductor products. Therefore, the miniaturization of the element has been developed among all the semiconductor products. Particularly, the memory cell is always the latest of the miniaturization technique.
The basic configuration of the micro memory cell is largely classified to two, which are a stack capacitor cell and a trench capacitor cell. However, as the miniaturization is advanced, there have been the following problems in both the stack capacitor cell and the trench capacitor cell.
In the stack capacitor cell, a storage node is formed on a substrate, and a cell plate is stacked on the storage node. Therefore, since the flatness of the layer formed on the substrate is deteriorated, the further miniaturization has become difficult.
In the trench capacitor cell, a cell to cell space was limited due to the leakage current which could result in punch through between adjacent trenches. Therefore, the further miniaturization has become difficult similarly to the stack capacitor cell.
Accordingly, a Buried Plate Trench capacitor cell (BPT cell) has been developed to eliminate these problems.
The BPT cell is disclosed in Japanese Patent Application KOKAI Publication No. 63-136558 and "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate-Wiring, T. Kaga et al., IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 35, No. 8, August 1988, p1257-p1263", etc.
The essential points of the BPT cell will be simply explained.
The BPT cell can exclude plates from the substrate to connect the plates formed in the trench in the substrate. Therefore, the flatness of the layer formed on the substrate is improved.
Since the storage node is formed in the trench and an oxide film collar is formed inside the trench to insulate the storage node from the substrate, the interval between the trenches can be reduced as compared with the trench capacitor cell.
The BPT cell is more easily miniaturized as compared with both the stack capacitor cell and the trench capacitor cell.
However, when the BPT cell is used in the actual dynamic RAM, several problems have been discovered.
Since the BPT cell connects the plates in the substrate, a wiring (hereinafter referred to as a "buried plate-wiring") is required in the substrate. Therefore, the actual dynamic RAM causes a problem of where of a chip a plate potential feeder for feeding a plate potential to buried plate-wiring via a plate potential supply-wiring is located.
The layout of the basic block (memory arrays, row circuits, column circuits, sense amplifiers, column gates, etc.) of the dynamic RAM has been substantially completed from the standpoint of obtaining the best integration density.
However, when the BPT cell is intended to be actually used for the dynamic RAM, the entirely new block of a connection node the plate potential supply-wiring to the buried plate-wiring is to be added to the substantially completed layout.
If the selection of the placing location is mistaken in the newly added block, it might disturb its integration density.
A method of connecting a plate potential supply-wiring to a buried plate-wiring was disclosed in Japanese Patent Application KOKAI Publication Nos. 63-136559 and 6-29485 and the above-described "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate-Wiring., T. Kaga et al., IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 35, No. 8, August 1988, p1257-p1263", but there has been no report at present as to where of the chip the connection node is provided.